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Imec Demonstrates World’s First Vertically Stacked Gate-all-Around Si Nanowire CMOS Transistors

These results advance the development of GAA nanowire MOSFETs.

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By: DAVID SAVASTANO

Contributing Editor, Coatings World and Ink World, Coatings World and Ink World Magazine

During IEEE’s International Electron Devices Meeting (IEDM) conference, imec reported for the first time the CMOS integration of vertically stacked gate-all-around (GAA) silicon nanowire MOSFETs. Key in the integration scheme is a dual-work-function metal gate enabling matched threshold voltages for the n- and p-type devices. Also, the impact of the new architecture on intrinsic ESD performance was studied, and an ESD protection diode is proposed. These results advance the development of GAA nanowire MOSFETs, which promise to succeed FinFETs in future technology nodes.
 
GAA nanowire transistors are promising candidates to succeed FinFETs in 7nm and beyond technology nodes. They offer optimal electrostatic control, thereby enabling ultimate CMOS device scaling. In a horizontal configuration, they are a natural extension of today’s mainstream FinFET technology. In this configuration, the drive current per footprint can be maximized by vertically stacking multiple horizontal nanowires. Earlier this year, imec scientists demonstrated GAA FETs based on vertically stacked 8nm diameter Si nanowires. These devices showed excellent electrostatic control, but were fabricated for n- and p-FETs separately.
 
Imec now reports on the CMOS integration of vertically stacked GAA Si nanowire MOSFETs, with matched threshold voltages for n- and p-type devices.
 
“GAA nanowire transistors enable ultimate CMOS device scaling, with low degree of added complexity compared to alternative scaling scenarios,” stated Dan Mocuta, director logic device and integration at imec.
 

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